Chemical mechanical polishing (CMP) methods are typically used in a number of aspects such as, for example, interlayer planarization in multi-layer wiring processes, shallow trench isolation of transistors, and the manufacture of silicon substrates or the manufacture of silicon on insulator (SOI) substrates. A target material which may be employed for use with a CMP method may contain one or more elements such as, for example, silicon (Si), silicon dioxide (SiO.sub.2), aluminum (Al), tungsten (W), and copper (Cu). The slurry which is used in a CMP process is usually selected according to the element or elements used as the target material. For example, if the target is an insulation layer containing a nitride or an oxide, an alkaline slurry is typically used. If the target material is formed from metal, it is generally preferable to use a weak acidic slurry.
Prior to carrying out the CMP step, deionized water is usually supplied to a polishing pad which has been wetted with deionized water or slurry. A wafer which is to be used in a micrelectronic (e.g., semiconductor) device is present on the polishing pad. The wafer may be polished by supplying polishing solution to the surface of the polishing pad, and applying the polishing solution to the wafer.
In attempting to polish the target, it is preferable to select a specific polishing solution based on the characteristics of the target. For example, when the target is an oxide layer, silica is typically used as a polishing agent. In this instance, an undiluted slurry solution which includes silica may be mixed with deionized water in a predetermined ratio, e.g., 1:1. The mixture may then be used as a polishing solution.
In general, there is often a difference in pH between the polishing solution and the deionized water used to wet the polishing pad. The pH of the polishing solution is typically alkaline (approximately 10-11) and the pH of the deionized water is usually neutral, i.e., 7. The difference in pH may be potentially disadvantageous in that the silica may coagulate to form abnormally large particles. As a result, the surface of the oxide layer may become damaged (e.g., .mu.-scratched) by virtue of the presence of the coagulated silica. This could be especially harmful in shallow trench isolation formation processes since active and non-active regions of semiconductor devices may become damaged. Thus, gate oxide layers and gate electrode lines could become adversely effected.
It is therefore an object of the present invention to provide methods of manufacturing microelectronic devices using chemical mechanical polishing techniques which address the difficulties described above.